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TraceWeave

Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM source, hierarchy, and connectivity to…

Install

$git clone https://github.com/gokeshenzhen/TraceWeave

Install command taken from the project's README or registry entry. Always review code before running it.

🐙 TraceWeave

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An MCP server for evidence-driven simulation debugging

TraceWeave is an MCP server for RTL / SoC debugging. It connects compile records, simulation logs, VCD/FSDB waveforms, and RTL source to your AI assistant, helping you work from a failed simulation to the relevant time, signals, and driving logic.

Use it with Claude Code, Codex, Copilot, or another MCP client. Describe the problem in natural language; the assistant uses tools to investigate, trace, and verify, with evidence you can review.

Use Cases · Installation · Client Setup · Start Debugging · Tool Quick Reference · FAQ · Documentation and Feedback

Use Cases

Problem How TraceWeave helps
A simulation times out or hangs, with no clear starting point Summarize failures and scan interface handshakes to narrow down the affected interfaces and time window
A scoreboard mismatch or different results between runs Compare failure records and waveforms, locate observed differences, and trace data and control sources on both sides
A signal becomes X/Z Follow drivers and review waveform history to check whether a register sampled and retained an unknown value
Packed buses are hard to read, or TL-UL requests are not completing Inspect address, data, and control fields individually, then check request/response handshakes, latency, and completion
Suspected ties, unconnected inputs, or magic-word conditions Statically scan source code for constant connections, open inputs, and constant comparisons as investigation leads; no simulation run or waveform required
A deep SoC hierarchy with many modules and interfaces Browse hierarchy on demand, locate instances and source files, and follow drivers, consumers, and connectivity paths
A debugging hypothesis needs evidence Sample by cycle and check timing conditions, handshake stability, and transaction completion

Supports VCS / Xcelium / Verilator simulation logs and VCD / FSDB / FST waveforms. Exported formal waveforms can also be queried; automatic artifact discovery currently supports JasperGold.

Optional FST support on Linux provides discovery, basic reads, fixed bit selections, expressions, cycle sampling, protocol and transaction analysis, cross-format comparison and X history. The summary lists the currently accepted tools.

Signal tracing (driver, load, and connectivity path queries) follows Verdi NPI → Source Graph → basic static analysis (Legacy Static) by default. It first queries the elaborated KDB; when NPI is unavailable or cannot provide a trustworthy result, it tries Source Graph without a commercial license, then falls back to basic static analysis where supported.

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