Tag

#degital-design

MCP servers, skills and plugins tagged “degital-design” on GitHub.

1 entries · real GitHub data

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#1Veriflow Cc
VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM…
Agent skill AI & LLM tooling Design & frontend