rtl-skills

A collection of Claude Code skills and agents that automate a full RTL/Verilog design flow — from a one-page IP requirement all the way to synthesized, tested, and documented hardware.

Drop these into a Verilog project and Claude can architect an IP, write the RTL, lint and simulate it, build a self-checking testbench, run regressions, debug failures, synthesize with Vivado, and produce documentation — each step driven by a focused, reviewable skill.

What's in here

Path	Contents
skills/	One folder per skill, each a SKILL.md defining the workflow, inputs, and outputs
agents/	Agent definitions (*.yaml) that bundle skills into roles with a model and turn budget
skills/shared/	Cross-skill contracts: coding style, module-doc format, hierarchy filelist rules
CLAUDE.md	Project instructions describing the directory layout and conventions a consuming project should follow

The design flow

ip_req.md
  │
  ├─[varch]────► ddoc/_req.md   (one per submodule) + rtl/<ip>_top.v skeleton
  ├─[vdesign]──► rtl/<module>.v backbone + ddoc/<module>_proposal.md + doc/<module>.md
  ├─[vfill]────► rtl/<module>.v full implementation + tb/<module>/ (lint + sim)
  ├─[vflow]────► flow_status.md            (live phase-completion snapshot, orchestration)
  ├─[vsynth]───► synth/<module>/           (Vivado: utilization, Fmax, power)
  ├─[vtestgen]─► tb/<ip>/                   (CPU-bus bench project + self-checking testcases)
  ├─[vtestrun]─► issue/<ip>/               (regression results + per-failure reports)
  ├─[vdebug]───► issue/<ip>/debug_*.md     (root-cause diagnosis, no fix proposed)
  └─[vdoc]─────► doc/<ip>.md               (full IP integration document)

Skills

Skill	Purpose
varch	Decompose an IP requirement into submodules, define interfaces, generate an architecture doc, per-module requirement files, and a top-level skeleton
vdesign	Generate a design proposal, module documentation, and an RTL backbone with //@ direction markers from a requirement file
vfill	Implement the Verilog from an approved proposal, then lint and simulate
vexplain	Generate documentation for any RTL module from its Verilog source
vdoc	Aggregate per-module documentation into a single IP-level document
vsynth	Synthesize a module or full IP with Vivado; report utilization, Fmax, and power
vtestgen	Scaffold a Makefile-driven, CPU-bus-controlled bench project and generate self-checking testcases
vtestrun	Run all testcases from tc_list.md, capture results, write per-failure issue reports
vdebug	Trace failing signals through the RTL hierarchy, classify root cause, write a debug report
vflow	Scan project state, write flow_status.md, and orchestrate the full flow end-to-end

Agents

Agents bundle one or more skills into a role with a fixed model and turn budget.